Digital Electronics | Semester 4 Core Notes
Semester 4 - Page 5: Digital Electronics. 29 numbered topics, highlighted rules, worked examples, answered exam questions, diagrams, truth/state tables and three complete Python 3 logic simulations. General common-core guide, not an official syllabus or hardware wiring instruction. Device details must come from the exact datasheet and your supervised lab rules.
Topic map
- Digital abstraction and real voltages
- Number systems and base conversion
- Signed representations and overflow
- BCD, Gray and error-detecting codes
- Logic gates and universal gates
- Boolean algebra and De Morgan laws
- SOP, POS and canonical forms
- Karnaugh maps and don't-cares
- Tabular minimization and hazards
- Half and full adders
- Subtractors and arithmetic blocks
- Multiplexers and demultiplexers
- Decoders and priority encoders
- Comparators, parity and ALU
- Latches and flip-flops
- JK, T and excitation tables
- Setup, hold and metastability
- Registers and shift registers
- Ripple counters and modulus
- Synchronous counters and worked alarm
- FSM design, Mealy and Moore
- Memories and programmable logic
- DAC principles and ideal resolution
- ADC architectures and quantization
- Sampling, aliases and converter limits
- Logic families, fan-out and noise margin
- HDL, simulation and synthesis
- Lab safety and systematic testing
- Exam revision checklist
1. Digital abstraction and real voltages
Digital logic represents values with defined voltage ranges, not magically exact zero and one volts. The logic abstraction hides analog behavior only within the device's specified operating limits.
Answer: Voltage, current, power, timing, pinout and environmental limits still apply.
2. Number systems and base conversion
Binary is base 2, hexadecimal base 16 and octal base 8. One hex digit represents four binary bits; assign place values before converting.
Answer: No. It changes the written width, not its numerical value.
3. Signed representations and overflow
Unsigned n-bit values range 0..2^n-1; two's-complement values range -2^(n-1)..2^(n-1)-1. Carry-out and signed overflow are different conditions.
Answer: Adding same-sign operands produces an opposite-sign fixed-width result.
4. BCD, Gray and error-detecting codes
BCD encodes each decimal digit in four bits; Gray code changes one bit between adjacent code words. Parity detects any odd number of bit flips but does not generally correct them.
Answer: No. Flipping two bits preserves parity.
5. Logic gates and universal gates
AND, OR, NOT, XOR, NAND and NOR define Boolean functions. NAND and NOR can each implement any Boolean function through composition. A truth table for n binary inputs has 2^n rows.
Answer: No. OR outputs one for input11; XOR outputs zero.
6. Boolean algebra and De Morgan laws
Boolean identities include idempotence, complement, absorption and distributivity. De Morgan swaps AND/OR while complementing all inputs; draw parentheses before transforming.
Answer: It confirms equivalence on every finite input combination, not just selected examples.
7. SOP, POS and canonical forms
A minterm is an AND term containing every variable exactly once; a maxterm is an OR term containing every variable. Canonical SOP lists rows where F=1; canonical POS lists rows where F=0.
Answer: No. Simplification commonly removes variables from product terms.
8. Karnaugh maps and don't-cares
K-maps use Gray-code adjacency; group powers of two, wrap across edges and never group diagonally. Groups remove changing variables. Don't-cares may be chosen to simplify only when those input cases truly are irrelevant.
Answer: No. Use it only when helpful; do not change required zero/one cells.
Three-variable K-map: F=sum m(1,3,5,7) BC columns: 00 01 11 10 A=0 0 1 1 0 A=1 0 1 1 0 Group the four 1s: only C stays 1.
K-map simplification truth-table check
from itertools import product
# Minterms 1,3,5,7: C is the least-significant input bit.
for a, b, c in product([0, 1], repeat=3):
index = 4*a + 2*b + c
original = int(index in {1, 3, 5, 7})
simplified = c
assert original == simplified
print("8 rows: F = C verified")
# De Morgan's two identities, all two-input cases.
for a, b in product([0, 1], repeat=2):
assert int(not (a and b)) == int((not a) or (not b))
assert int(not (a or b)) == int((not a) and (not b))
print("4 rows: both De Morgan laws verified")
Checked output:
8 rows: F = C verified 4 rows: both De Morgan laws verified
9. Tabular minimization and hazards
Quine-McCluskey combines implicants differing in one bit and selects a covering set. Static hazards can occur when unequal path delays create a brief wrong output even though the Boolean function is correct.
Answer: No. Logical minimization and timing/hazard design are different objectives.
10. Half and full adders
A half-adder has sum A XOR B and carry A AND B. A full-adder includes carry-in: sum=A XOR B XOR Cin; carry=AB+A Cin+B Cin. Cascading creates a ripple-carry adder.
Answer: Each stage may wait for the previous stage's carry propagation.
Full-adder truth table
from itertools import product
print("A B Cin | Sum Carry")
for a, b, cin in product([0, 1], repeat=3):
total = a + b + cin
s = a ^ b ^ cin
carry = (a & b) | (a & cin) | (b & cin)
assert total == s + 2 * carry
print(a, b, cin, "|", s, carry)
Checked output:
A B Cin | Sum Carry 0 0 0 | 0 0 0 0 1 | 1 0 0 1 0 | 1 0 0 1 1 | 0 1 1 0 0 | 1 0 1 0 1 | 0 1 1 1 0 | 0 1 1 1 1 | 1 1
11. Subtractors and arithmetic blocks
A half-subtractor difference is A XOR B and borrow=NOT A AND B. Fixed-width subtraction can use addition of the two's-complement negation. Carry-lookahead computes carry conditions in parallel groups.
Answer: No. Adder-based subtraction may use an inverted borrow convention; state the circuit's definition.
12. Multiplexers and demultiplexers
A multiplexer selects one of many inputs; a demultiplexer routes one input to a selected output. A 2:1 mux has Y=NOT(S)I0+S I1; n select bits choose up to2^n inputs.
Answer: Not by itself. It is combinational selection.
13. Decoders and priority encoders
A decoder activates an output based on an input code, subject to enables and active-high/low conventions. A priority encoder resolves multiple asserted inputs by a defined ranking.
Answer: Only if its stated input contract guarantees that; otherwise a priority rule is needed.
14. Comparators, parity and ALU
A magnitude comparator reports less/equal/greater for the specified representation. Parity uses XOR chains; an ALU chooses arithmetic/logic operations under control inputs.
Answer: The same bit patterns can have different numerical orderings.
15. Latches and flip-flops
A latch is level-sensitive; an edge-triggered flip-flop samples near a specified clock edge. A D element stores its input subject to timing. An SR latch's forbidden condition depends on NAND/NOR and input polarity.
Answer: No. Their transparency and sampling behavior differ.
16. JK, T and excitation tables
JK inputs00 hold,01 reset,10 set,11 toggle for the common active-high edge-triggered model. A T flip-flop toggles when T=1. Excitation tables ask which inputs produce a desired state transition.
Answer: Characteristic maps input/current state to next state; excitation maps desired transition to possible inputs.
17. Setup, hold and metastability
Data must remain stable for specified setup/hold windows around capture. Violations can cause metastability; synchronizers reduce failure probability but cannot make it mathematically zero.
Answer: No. It needs timing and device-level reasoning.
18. Registers and shift registers
A register stores a group of bits; shift registers transfer bits on clock events. SISO,SIPO,PISO and PIPO describe serial/parallel inputs/outputs, not automatically a specific physical pinout.
Answer: Otherwise the same input stream can produce different displayed bit orders.
19. Ripple counters and modulus
Ripple counters clock successive stages from earlier outputs, so transitions propagate. A counter's modulus is the number of states in its repeating cycle; n bits permit at most2^n states.
Answer: Outputs do not change simultaneously, so intermediate bit patterns can briefly appear.
20. Synchronous counters and worked alarm
A synchronous counter clocks storage stages together and derives next-state inputs from current state. For two-bit up-counting, D0=NOT Q0 and D1=Q1 XOR Q0; alarm=Q1 AND Q0.
Answer: No. Clock-to-Q, logic delay, skew and timing constraints remain.
[00] -> [01] -> [10] -> [11] ^ | +-----------------------+ D0 = NOT Q0 D1 = Q1 XOR Q0 Alarm = Q1 AND Q0
Two-bit synchronous counter
q1, q0 = 0, 0
print("Q1Q0 Alarm Next")
for _ in range(4):
d1, d0 = q1 ^ q0, 1 - q0
print(f"{q1}{q0} {q1 & q0} {d1}{d0}")
q1, q0 = d1, d0
assert (q1, q0) == (0, 0)
Checked output:
Q1Q0 Alarm Next 00 0 01 01 0 10 10 0 11 11 1 00
21. FSM design, Mealy and Moore
A finite-state machine has state transitions and outputs. Moore outputs depend on state; Mealy outputs depend on state and current inputs. Derive a state table, encoding, next-state logic and reset behavior.
Answer: No. Combinational dependence on input can affect glitches/timing unless explicitly registered.
22. Memories and programmable logic
RAM and ROM families differ in write behavior, volatility and technology. SRAM and DRAM both normally need power to retain data; DRAM also needs refresh. PLA/PAL/CPLD/FPGA implement programmable logic with different structures.
Answer: No. PROM,EPROM,EEPROM and flash have different programming/erase rules.
23. DAC principles and ideal resolution
A DAC maps digital code to an analog level. Binary-weighted and R-2R networks are common teaching designs; output range, reference, settling and error specifications matter.
Answer: Transfer conventions differ. State whether full-scale refers to reference or the highest code output.
24. ADC architectures and quantization
An ADC maps sampled analog values to digital codes. Flash uses comparator banks, SAR searches by successive approximation, and dual-slope integrates over time. Ideal n-bit quantization has2^n bins under the stated range convention.
Answer: No. Noise,offset,gain,linearity and reference errors can dominate.
Analog signal -> filter/sample -> ADC Digital code -> DAC -> analog output
25. Sampling, aliases and converter limits
Sampling must account for signal bandwidth and filtering. For a strictly band-limited signal with highest frequency B, sampling above2B supports ideal reconstruction; practical systems need anti-alias filtering and margin.
Answer: No. Phase and boundary issues make a strict margin and practical design necessary.
26. Logic families, fan-out and noise margin
Logic families specify voltage/current thresholds, propagation, power and loading. Fan-out depends on both source/sink current limits and dynamic capacitive loading. Noise margins compare guaranteed output levels with required input levels.
Answer: No. Threshold and absolute-maximum limits must both be checked.
27. HDL, simulation and synthesis
A hardware description models concurrent circuits; synthesis supports a subset and maps it into hardware. Testbenches can use simulation-only constructs. Blocking/nonblocking choices and reset rules depend on the HDL and process type.
Answer: No. Synthesis,implementation,timing analysis and hardware checks are separate stages.
28. Lab safety and systematic testing
Read the exact device datasheet for supply,pinout,limits and reset before wiring. Do not leave inputs floating unless explicitly permitted. Simulate function, then measure timing and document actual results safely.
Answer: No. Verify its exact part and datasheet; power off before rewiring under lab rules.
29. Exam revision checklist
Start from width/signedness or the truth/state table, derive logic, then address timing and electrical assumptions. Separate combinational functions from stateful behavior and ideal simulations from hardware evidence.
Answer: Specification,truth/state table,simplification,circuit or HDL,correctness trace and timing/device limits.
Two-input truth table
| A | B | AND | OR | XOR | NAND | NOR |
|---|---|---|---|---|---|---|
| 0 | 0 | 0 | 0 | 0 | 1 | 1 |
| 0 | 1 | 0 | 1 | 1 | 1 | 0 |
| 1 | 0 | 0 | 1 | 1 | 1 | 0 |
| 1 | 1 | 1 | 1 | 0 | 0 | 0 |
Stored-state element comparison
| Element | Common input rule | Timing caution |
|---|---|---|
| D | NextQ=D at capture | Setup/hold around active edge |
| T | Toggle if T1;hold if T0 | Edge behavior follows device |
| JK | 00hold,01reset,10set,11toggle | Model/polarity must be stated |
| SR NOR latch | Active-high set/reset | Both asserted is forbidden |
| D latch | Transparent while enabled | Not edge-triggered |
Computed numeric reference
| Quantity | Result | Assumption |
|---|---|---|
| 101101 binary | 45 decimal;2D hex | Unsigned interpretation |
| 4-bit two's complement | -8..7 | Fixed width4 |
| 10 address bits x8 data bits | 1024 bytes | One8-bit word per address |
| 8-bit converter step | 0.01953125V | 5/256V per code/bin |
| DAC code128 | 2.5V | Ideal unipolar5V reference |
| DAC code255 | 4.98046875V | Highest code below reference |
| 3-bit flash comparators | 7 | Conventional2^n-1 thresholds |
Last-minute design checklist
State input/output conventions, then truth/state table, Boolean simplification, circuit/HDL, reset and timing constraints. Check every finite truth-table row. For physical hardware, confirm exact part number, supply, thresholds, current loading and test procedure separately.
Resources and sources
Teaching references support the common principles. Examples, diagrams and simulations here are original. No named IC or physical build is claimed tested.
Comments
Post a Comment